Controller, memory system including the controller, and method of operating the memory system

ABSTRACT

The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean patent application number 10-2019-0025327, filed on Mar. 5, 2019,in the Korean Intellectual Property Office, the entire disclosure ofwhich is incorporated herein by reference.

BACKGROUND 1. Technical Field

The present disclosure generally relates to a controller, a memorysystem including the controller, and a method of operating the memorysystem, and more particularly, to a controller, a memory systemincluding the controller, and a method of operating the memory system,related to allocating memory blocks included in a memory systemaccording to a request of a host.

2. Related Art

An electric system may include a memory system in which data is stored,and a host that stores data in the memory system or reads stored data.

The memory system may include a storage device in which data issubstantially stored and a controller that controls the storage device.The storage device may include at least one memory device.

The memory device may be divided into a volatile memory device and anonvolatile memory device. The volatile memory device is a memory devicein which stored data is lost when power supply is interrupted, and thenonvolatile memory device is a memory device in which stored data isretained even though power supply is interrupted.

Of these, the nonvolatile memory device is widely used in a portableelectronic system because of characteristics of retaining data withoutpower supply and characteristics of ease of miniaturization and largecapacity. For example, the nonvolatile memory device is used in anelectronic system such as a cellular phone, a notebook, a camcorder, anda digital camera, and is used as a main storage device of a solid statedrive (SSD) that is a storage system capable of replacing a hard disk.

The host may communicate with the memory system using at least one ofvarious communication methods such as universal serial bus (USB), serialAT attachment (SATA), serial attached SCSI (SAS), high speed interchip(HSIC), small computer system interface (SCSI), peripheral componentinterconnection (PCI), PCI express (PCIe), nonvolatile memory express(NVMe), universal flash storage (UFS), secure digital (SD), multimediacard (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM),registered DIMM (RDIMM), and load reduced DIMM (LRDIMM).

Recently, as a range of use of an electronic system is widening, thehost may request a large capacity of storage space allocation to thememory system.

In general, the host may request allocation using a logical blockaddress of the memory system. For example, the host may transmit startand end addresses of the logical block address (LBA) to the memorysystem in order to receive the allocation of a required storagecapacity, and the memory system may allocate memory blocks correspondingto the logical block address received from the host.

However, due to the large capacity of the memory system, the number ofbits indicating the logical block address is increasing, which mayincrease an operation time of mapping a logical block address and aphysical block address in the memory system.

SUMMARY

A controller according to an embodiment of the present disclosure mayinclude an allocation manager configured to determine whether a hostidentification (ID) output from a host is an allocable ID, an addressmanager configured to perform an allocation operation using the host IDto select logical blocks corresponding to the host ID when the host IDis received from the allocation manager, and output an address of thelogical blocks as an allocation address, and a map table componentconfigured to store a map table in which logical block addresses andphysical block addresses are respectively mapped, select a logical blockaddress corresponding to the allocation address, and output the physicalblock address mapped to the selected logical block address.

A controller according to an embodiment of the present disclosure mayinclude a processor configured to map physical block addressescorresponding to free memory blocks to logical block addresses so thatthe free memory blocks that are operable simultaneously with each otherare included in the same tree, an address allocator configured toperform an allocation operation based on a configuration of the tree toselect logical blocks corresponding to a host ID and output addresses ofthe free memory blocks mapped to addresses of the logical blocks, and amemory interface that accesses physical blocks corresponding toaddresses of the free memory blocks.

A memory system according to an embodiment of the present disclosure mayinclude a plurality of memory blocks, and a controller configured toreceive a host ID according to a host ID policy in which the memoryblocks are divided into logical block units, calculate an allocationaddress based on the received host ID, and access allocated memoryblocks among the memory blocks according to physical block addressesmapped to the allocation address.

A method of operating a memory system according to an embodiment of thepresent disclosure may include calculating a start node and the numberof logical blocks by performing an allocation operation using a host IDwhen the host ID divided into logical block units is received,generating an address of the logical blocks allocated according to thestart node and the number as an allocation address, detecting a physicalblock address mapped to the allocation address, and allocating memoryblocks according to the physical block address.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for describing a memory system according to thepresent disclosure.

FIG. 2 is a diagram for describing a controller of FIG. 1.

FIG. 3 is a diagram for describing a die of FIG. 1.

FIG. 4 is a diagram for describing a memory cell array of FIG. 3.

FIGS. 5 and 6 are diagrams for describing a memory block of athree-dimensional structure according to a first embodiment.

FIGS. 7 and 8 are diagrams for describing a memory block of athree-dimensional structure according to a second embodiment.

FIG. 9 is a diagram for describing an address allocator of FIG. 2.

FIG. 10 is a flowchart for describing a memory allocation operationaccording to an embodiment of the present disclosure.

FIG. 11 is a flowchart for describing a de-allocation operationaccording to an embodiment of the present disclosure.

FIG. 12 is a diagram for describing an allocation manager of FIG. 9.

FIG. 13 is a diagram for describing a host ID and an allocation space.

FIG. 14 is a diagram for describing a method of allocating a physicalblock matched with a logical block.

FIG. 15 is a diagram for describing a memory allocation method accordingto an embodiment of the present disclosure.

FIG. 16 is a flowchart for describing an example of an operation used inthe memory allocation operation of FIG. 15.

FIG. 17 is a first embodiment of the memory allocation operation towhich the operation of FIG. 16 is applied.

FIG. 18 is a second embodiment of the memory allocation operation towhich the operation of FIG. 16 is applied.

FIGS. 19 and 20 are diagrams for describing the memory allocation methodaccording to another embodiment of the present disclosure.

FIG. 21 is a flowchart for describing an example of the operation usedin the memory allocation method of FIG. 20.

FIG. 22 is a diagram for describing a first embodiment of a memoryallocation operation to which the operation of FIG. 21 is applied.

FIG. 23 is a diagram for describing a second embodiment of the memoryallocation operation to which the operation of FIG. 21 is applied.

FIG. 24 is a diagram for describing a host ID policy for requestingmemory allocation from a host to a memory system.

FIG. 25 is a diagram for describing embodiments of the host ID policy ofFIG. 24.

FIG. 26 is a diagram for describing an embodiment of a second host IDpolicy among the embodiments described with reference to FIG. 25.

FIG. 27 is a diagram for describing an operation of a map tablecomponent of FIG. 9.

FIG. 28 is a flowchart for describing an example of an operation ofcalculating a host ID using a start node.

FIG. 29 is a diagram for describing an embodiment of a method ofcalculating the host ID to which the operation of FIG. 28 is applied.

FIGS. 30 to 33 are diagrams for describing another embodiment of thememory system including the controller shown in FIG. 2.

DETAILED DESCRIPTION

The advantages and features of the present disclosure, and a method foraccomplishing the advantages and features will be described throughembodiments that are described in detail below with reference to theaccompanying drawings. However, the present disclosure is not limited tothe embodiments described herein but may be embodied in other forms. Thepresent embodiments are provided to describe the technical spirit of thepresent disclosure in detail to those skilled in the art to which thepresent disclosure is pertains so that those skilled in the art mayeasily implement the technical spirit of the present disclosure.

Throughout the specification, in a case in which a portion is“connected” to another portion, the case includes not only a case inwhich the portion is “directly connected” to the other portion but alsoa case in which the portion is “indirectly connected” to the otherportion with another element interposed therebetween. Throughout thespecification, in a case in which a portion includes an element, thecase means that the portion may include other elements without excludingother elements unless specifically stated otherwise.

An embodiment of the present disclosure may provide a controller, amemory system including the controller, and a method of operating thememory system, in which the memory system itself may manage anallocation space.

The present technology may efficiently manage a memory area of thememory system since the memory system itself rather than the hostmanages the allocation space. In addition, the present technology mayreduce a memory allocation operation time according to a request of thehost, by reducing the number of bits used for the allocation spaceoperation.

FIG. 1 is a diagram for describing a memory system according to thepresent disclosure.

Referring to FIG. 1, the memory system 1000 may include a storage device1100 in which data is stored and a controller 1200 that controls thestorage device 1100.

The storage device 1100 may include a plurality of dies D1 to Dk (k is apositive integer). The dies D1 to Dk may be implemented as a volatilememory device in which the stored data is lost when power supply isinterrupted or a nonvolatile memory device in which the stored data isretained even though the power supply is interrupted. In the followingembodiment, a memory system including the dies D1 to Dk implemented asthe nonvolatile memory device will be described as an example. Thenonvolatile memory device may be a NAND flash memory device.

The storage device 1100 may communicate with the controller 1200 througha plurality of channels CH1 to CHi (i is a positive integer). Forexample, the dies D1 to Dk included in the storage device 1100 mayreceive a command, an address, data, and the like from the controller1200 and output data to the controller 1200 through the channels CH1 toCHi.

The controller 1200 may control the storage device 1100 according to arequest received from a host 2000 and may output the data read from thestorage device 1100 to the host 2000. For example, when the controller1200 receives a program request and data from the host 2000, thecontroller 1200 may store the received data in the storage device 1100.When the controller 1200 receives a read request and a logical blockaddress from the host 2000, the controller 1200 may perform a readoperation according to a physical block address mapped to the logicalblock address, and may output the read data to the host 2000.

In addition, the controller 1200 may perform a background operationcapable of managing the storage device 1100 even though there is norequest from the host 2000. For example, the controller 1200 may performfunctions such as garbage collection and wear leveling, and may performvarious functions for efficiently managing the storage device 1100.

In addition, the controller 1200 may allocate or release a memory inconsideration of a state of the storage device 1100 according to anallocation request or a de-allocation request from the host 2000. Tothis end, the host 2000 may request an allocation capacity in a form ofa host identification (ID), and the controller 1200 may allocate memoryblocks included in the storage device 1100 according to an operationprocess that is embedded in the controller 1200.

The host 2000 may communicate with the memory system 1000 using aninterface protocol such as peripheral component interconnect express(PCIe), advanced technology attachment (ATA), serial ATA (SATA),parallel ATA (PATA), serial attached SCSI (SAS), or a nonvolatile memoryexpress (NVMe). The storage interface 2200 is not limited to the aboveexample and may include various interfaces such as universal serial bus(USB), multi-media card (MMS), enhanced small disk interface (ESDI).

FIG. 2 is a diagram for describing the controller of FIG. 1.

Referring to FIG. 2, the controller 1200 may include a processor 210, anaddress allocator 220, and a memory interface 230.

The processor 210 may receive an allocation request AC_RQ and a host IDH # from the host 2000 and may perform an allocation process accordingto the allocation request AC_RQ. For example, the processor 210 maytransmit the host ID H # to the address allocator 220 according to theallocation request AC_RQ, and may output an allocation completion signalCOMP or a fail signal FA to the host 2000 in response to an allocationimpossible signal IMP.

The address allocator 220 may determine whether it is allocableaccording to the host ID H # received from the processor 210 and outputthe allocation completion signal FIN or the allocation impossible signalIMP, and when the memory allocation is possible, the address allocator220 may output an allocated physical block address P_ADD. The addressallocator 220 may determine whether the host ID H # is an allocable ID,and when the host ID H # is unallocable, the address allocator 220 mayoutput the allocation impossible signal IMP. For example, theunallocable case may include a case in which the host ID H # exceeds acapacity of the storage device 1100 or the number of allocable freememory blocks is less than a requested number. The allocable case mayinclude a case in which the host ID H # does not exceed the capacity ofthe storage device 1100 and a previously allocated log information ispresent or the number of allocable free memory blocks is equal to orgreater than the requested number.

The memory interface 230 may select the channel CH # and the die D #according to the physical block address P_ADD received from the addressallocator 220 and access the selected die.

Each of the configurations described above with reference to FIGS. 1 and2 will be described below as follows.

FIG. 3 is a diagram for describing the die of FIG. 1.

Since the first to k-th dies D1 to Dk may be configured to be identicalto each other, the k-th die Dk will be described as an example in FIG.3.

Referring to FIG. 3, the k-th die Dk may include a memory cell array 110in which data is stored, peripheral circuits 120, 130, 140, 150 and 160that perform a program, read, or erase operation, and control logic 170that controls the peripheral circuits 120-160.

The memory cell array 110 may include a plurality of memory blocks inwhich data is stored. Each of the memory blocks includes a plurality ofmemory cells, and the memory cells may be implemented as atwo-dimensional structure arranged parallel to a substrate or athree-dimensional structure stacked on the substrate in a verticaldirection.

The peripheral circuits 120 to 160 may include a voltage generator 120,a row decoder 130, a page buffer group 140, a column decoder 150, and aninput/output circuit 160.

The voltage generator 120 may generate and output operation voltages Voprequired for various operations in response to an operation signalOP_SIG. For example, the voltage generator 120 may generate and output aprogram voltage, a verification voltage, a read voltage, a pass voltage,and an erase voltage.

The row decoder 130 may select one memory block among the memory blocksincluded in the memory cell array 110 according to a row address RADDand transmit operation voltages Vop through local lines LL of theselected memory block.

The page buffer group 140 may include a plurality of page buffersconnected to bit lines BL and may temporarily store data at a time of aprogram or read operation in response to a page buffer control signalPBSIG. Each of the page buffers may include a plurality of latches fortemporarily storing data at a time of program, read, and verificationoperations.

The column decoder 150 may be connected to the page buffer group 140through column lines CL and may be connected to the input/output circuit160 through data lines DL. For example, the column decoder 150 maytransfers data received through the data lines DL to the page buffergroup 140 at the time of the program operation or transfer data receivedthrough the column lines CL at the time of the read operation to theinput/output circuit 160 through the data lines DL.

The input/output circuit 160 may be connected to the controller 1200through input/output lines and may input/output a command CMD, anaddress ADD, and data DATA through the input/output lines. For example,at the time of the program operation, the input/output circuit 160 maytransfer the command CMD and the address ADD received from thecontroller 1200 to the control logic 170 and transfer the data DATA tothe column decoder 150. The column decoder 150 may sequentially transmitthe data DATA to the page buffer group 140 according to a column addressCADD. At the time of the read operation, the input/output circuit 160may output the data DATA received from the column decoder 150 to thecontroller 1200.

FIG. 4 is a diagram for describing the memory cell array of FIG. 3.

Referring to FIG. 4, the memory cell array 110 may include a pluralityof memory blocks MB1 to MBk. The memory blocks MB1 to MBk may include aplurality of memory cells and may share bit lines (BL of FIG. 2) witheach other.

The memory block will be described in below as follows.

FIGS. 5 and 6 are diagrams for describing a memory block of athree-dimensional structure according to a first embodiment. FIG. 5 is aperspective view of the memory block, and FIG. 6 is a circuit diagram ofthe memory block.

Referring to FIG. 5, the k-th memory block MBk implemented in athree-dimensional structure may be formed in a vertical (Z direction) Ishape on a substrate, and may include a plurality of cell strings STarranged between bit lines BL and source lines SL. Alternatively, thecell strings ST may be connected to a well instead of the source lineSL. Such a structure is also referred to as bit cost scalable (BiCS).For example, when the source line SL is horizontally formed on thesubstrate, the cell strings ST having the BiCS structure may be formedin the direction (Z direction) perpendicular to an upper portion thesource line SL.

For example, the cell strings ST may be arranged in a first direction (Xdirection) and a second direction (Y direction), respectively. The cellstrings ST may include source select lines SSL, word lines WL, and drainselect lines DSL that are stacked and spaced apart from one another. Thenumber of the source select lines SSL, the word lines WL, and the drainselect lines DSL is not limited to the number shown in the drawing. Thecell strings ST may include vertical channel films CH vertically passingthrough the source select lines SSL, the word lines WL, and the drainselect lines DSL, and the bit lines BL that are in contact with an upperportion of the vertical channel films CH protruded to an upper portionof the drain select lines DSL and extending in the second direction (Ydirection). The memory cells may be formed between the word lines WL andthe vertical channel films CH. A contact plug CT may be further formedbetween the bit lines BL and the vertical channel films CH.

Referring to FIG. 6, the first memory block MB1 may include a pluralityof cell strings ST11′ to ST1 m′ and ST21′ to ST2 m′. Each of theplurality of cell strings ST11′ to ST1 m′ and ST21′ to ST2 m′ may extendalong the vertical direction (Z direction), and m cell strings may bearranged in a row direction (X direction) in the first memory block MB1.In FIG. 6, two cell strings are arranged in a column direction (Ydirection). However, this is for convenience of description, and threeor more cell strings may be arranged in the column direction (Ydirection).

Each of the plurality of cell strings ST11′ to ST1 m′ and ST21′ to ST2m′ may include at least one source select transistor SST, first to n-thmemory cells MC1 to MCn, and at least one drain select a transistor DST.

The source select transistor SST of each of the cell strings may beconnected between the source line SL and the memory cells MC1 to MCn.The source select transistors SST of the cell strings arranged in thesame row may be connected to the same source select line SSL1 or SSL2.The source select transistors SST of the cell strings ST11′ to ST1 m′arranged in a first row may be connected to a first source select lineSSL1. The source select transistors of the strings ST21′ to ST2 m′arranged in a second row may be connected to a second source select lineSSL2. As another embodiment, the source select transistors of thestrings ST11′ to ST1 m′ and ST21′ to ST2 m′ may be commonly connected toone source select line.

The first to n-th memory cells MC1 to MCn of each of the cell stringsmay be connected in series between the source select transistor SST andthe drain select transistor DST. Gates of the first to n-th memory cellsMC1 to MCn may be connected to the first to n-th word lines WL1 to WLn,respectively. In addition, at least one of the first to n-th memorycells MC1 to MCn may be used as a dummy memory cell.

The drain select transistor DST of the cell strings may be connectedbetween the bit line and the memory cells MC1 to MCn. The drain selecttransistors DST of the cell strings arranged in the row direction may beconnected to a drain select line extending in the row direction. Thedrain select transistors DST of the cell strings CS11′ to CS1 m′ of thefirst row may be connected to a first drain select line DSL1. The drainselect transistors DST of the cell strings CS21′ to CS2 m′ of the secondrow may be connected to a second drain select line DSL2.

FIGS. 7 and 8 are diagrams for describing a memory block of athree-dimensional structure according to a second embodiment. FIG. 7 isa perspective view of the memory block, and FIG. 8 is a circuit diagramof the memory block.

Referring to FIG. 7, the k-th memory block MBk implemented in athree-dimensional structure may be formed in a U shape in a verticaldirection (Z direction) on a substrate, and may include a pair of sourcestrings ST_S and drain strings ST_D connected between the bit lines BLand the source lines SL. The source strings ST_S and the drain stringsST_D may be connected to each other through a pipe gate PG to form aU-shaped structure. The pipe gate PG may be formed in a pipeline PL. Forexample, the source strings ST_S may be vertically formed between thesource lines SL and the pipeline PL, and the drain strings ST_D may bevertically formed between the bit lines BL and the pipelines PL. Such astructure is also referred to as pipe-shaped bit cost scalable (P-BiCS).

For example, the drain strings ST_D and the source strings ST_S may bearranged in the first direction (X direction) and the second direction(Y direction), respectively, and the drain strings ST_D and the sourcestrings ST_S may be alternately arranged along the second direction Y.The drain strings ST_D may include the word lines WL and the drainselect lines DSL that are stacked and spaced apart from each other, anddrain vertical channel films D_CH vertically passing through the wordlines WL and the drain select lines DSL. The source strings ST_S mayinclude the word lines WL and the source select lines SSL that arestacked and spaced apart from each other, and source vertical channelfilms S_CH vertically passing through the word lines WL and the sourceselect lines SSL. The drain vertical channel films D_CH and the sourcevertical channel films S_CH may be connected to each other by the pipegate PG in the pipeline PL. The bit lines BL may be in contact with anupper portion of the drain vertical channel films D_CH protruded to theupper portion of the drain select line DSL and may extend in the seconddirection (Y direction).

Referring to FIG. 8, the first memory block MB1 may include a pluralityof cell strings ST11 to ST1 m and ST21 to ST2 m. Each of the pluralityof cell strings ST11 to ST1 m and ST21 to ST2 m may be formed in a Ushape. In the first memory block MB1, m strings may be arranged in therow direction (X direction). In FIG. 8, two cell strings are arranged inthe column direction (Y direction), but this is for convenience ofdescription, and three or more cell strings may be arranged in thecolumn direction (Y direction).

Each of the plurality of cell strings ST11 to ST1 m and ST21 to ST2 mmay include at least one source select transistor SST, first to n-thmemory cells MC1 to MCn, a pipe transistor PT, and at least one drainselect transistor DST.

The source and drain select transistors SST and DST and the memory cellsMC1 to MCn may have similar structures. For example, each of the sourceand drain select transistors SST and DST and the memory cells MC1 to MCnmay include a channel film, a tunnel insulating film, a charge trapfilm, and a blocking insulating film. For example, a pillar forproviding the channel film may be provided in each string. For example,a pillar for providing at least one of the channel film, the tunnelinsulating film, the charge trap film, and the blocking insulating filmmay be provided in each string.

The source select transistor SST of each of the cell strings may beconnected between the source line SL and the memory cells MC1 to MCp.

As an embodiment, the source select transistors of the strings arrangedin the same row may be connected to the source select line extending inthe row direction, and the source select transistors of the cell stringsarranged in different rows may be connected to different source selectlines. In FIG. 8, the source select transistors of the strings ST11 toST1 m of the first row may be connected to the first source select lineSSL1. The source select transistors of the cell strings ST21 to ST2 m ofthe second row may be connected to the second source select line SSL2.

As another embodiment, the source select transistors of the cell stringsST11 to ST1 m and ST21 to ST2 m may be commonly connected to one sourceselect line.

The first to n-th memory cells MC1 to MCn of the cell strings may beconnected between the source select transistor SST and the drain selecttransistor DST.

The first to n-th memory cells MC1 to MCn may be divided into first top-th memory cells MC1 to MCp and (p+1)-th to n-th memory cells MCp+1 toMCn. The first to p-th memory cells MC1 to MCp may be sequentiallyarranged in the vertical direction (Z direction), and may be connectedin series between the source select transistor SST and the pipetransistor PT. The (p+1)-th to n-th memory cells MCp+1 to MCn may besequentially arranged in the vertical direction (Z direction), and maybe connected in series between the pipe transistor PT and the drainselect transistor DST. The first to p-th memory cells MC1 to MCp and the(p+1)-th to n-th memory cells MCp+1 to MCn may be connected to eachother through the pipe transistor PT. Gates of the first to n-th memorycells MC1 to MCn of each string may be connected to the first to then-th word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n-th memory cells MC1 toMCn may be used as a dummy memory cell. When the dummy memory cell isprovided, a voltage or a current of a corresponding string may be stablycontrolled. A gate of the pipe transistor PT of each string may beconnected to the pipeline PL.

The drain select transistor DST of each string may be connected betweenthe bit line and the memory cells MCp+1 to MCn. The strings arranged inthe row direction may be connected to the drain select line extending inthe row direction. The drain select transistors of the strings ST11 toST1 m of the first row may be connected to the first drain select lineDSL1. The drain select transistors of the strings ST21 to ST2 m of thesecond row may be connected to the second drain select line DSL2.

The cell strings arranged in the column direction may be connected tothe bit lines extending in the column direction. In FIG. 8, the stringsST11 and ST21 of the first column may be connected to the first bit lineBL1. The strings ST1 m and ST2 m of the m-th column may be connected tothe m-th bit line BLm.

Among the cell strings arranged in the row direction, the memory cellsconnected to the same word line may configure one page. For example, thememory cells connected to the first word line WL1 among the strings ST11to ST1 m of the first row may configure one page. The memory cellsconnected to the first word line WL1 among the strings ST21 to ST2 m ofthe second row may configure another page. The cell strings arranged inone row direction will be selected by selecting any one of the drainselect lines DSL1 and DSL2. One page of the selected cell strings willbe selected by selecting any one of the word lines WL1 to WLn.

FIG. 9 is a diagram for describing the address allocator of FIG. 2.

Referring to FIG. 9, the address allocator 220 may include an allocationmanager 310, an address manager 320, and a map table component 330.

The allocation manager 310 may determine whether the host ID H # is theallocable ID. For example, when the memory allocation is impossibleaccording to the host ID H #, the allocation manager 310 may output theallocation impossible signal IMP. When the memory allocation is possibleaccording to the host ID H # and thus the memory allocation is completedby the allocation operation, the allocation manager 310 may output theallocation completion signal FIN. Whether or not the allocation ispossible may be determined according to whether the host ID H # receivedfrom the host 2000 conforms to a host ID policy prescribed between thehost 2000 and the memory system 1000, whether or not the capacity of thememory of which the allocation is requested is allocable capacity, orthe like.

When the memory allocation is possible, the allocation manager 310 maytransmit the host ID H # to the address manager 320, and the addressmanager 320 may perform the allocation operation using the host ID H #to allocate memory areas. An address of the allocated memory area may beoutput as an allocation address A_LB. When the allocation address A_LBis received, the allocation manager 310 may temporarily store theallocation address A_LB mapped to the host ID H # and output theallocation completion signal FIN. Here, the reason why the allocationaddress A_LB mapped to the host ID H # is temporarily stored is toreduce an operation time of the memory system 1000 by omitting thememory allocation operation and using stored log information since theallocation is requested again with the same capacity after theallocation of the allocated memory area is released. In addition, theallocation manager 310 may output the allocation address A_LB to the maptable component 330 when the allocation of the memory area is completed.

When the address manager 320 receives the host ID H # from theallocation manager 310, the address manager 320 may perform the memoryallocation operation to output the allocation address A_LB. For example,when the host ID H # is received, the address manager 320 may perform anoperation using the host ID H # and output the allocation address A_LBbased on values generated in the operation. The specific operation ofthe memory allocation operation performed by the address manager 320will be described later.

The map table component 330 may include registers in which a map tablein which the logical block address and the physical block address aremapped is stored. When the allocation address A_LB is received, the maptable component 330 may select a physical block address P_ADDcorresponding to the allocation logical block with reference to the maptable stored in the registers, and output the selected physical blockaddress P_ADD.

FIG. 10 is a flowchart for describing the memory allocation operationaccording to an embodiment of the present disclosure.

Referring to FIG. 10, the host 2000 may output the allocation request tothe memory system 1000 together with the host ID H # corresponding to arequired capacity (S101). There are various cases in which the host 2000requests the memory allocation. For example, when securing a capacityrequired for the program operation, the host 2000 may request the memoryallocation before outputting the program request. Alternatively, evenwhen the memory area is divided into a plurality of areas to be usedaccording to user's needs, the host 2000 may request the memoryallocation. In addition, the host 2000 may request the memory allocationin various cases, such as a usage purpose or a usage method of thememory area.

The host 2000 may request the memory allocation as an ID type instead ofa logical block address type. The host ID H # will be described belowwith reference to FIG. 13.

When the host 2000 outputs the host request and the host ID H # to thememory system 1000, the controller 1200 included in the memory system1000 may determine whether the received host ID H # is suitable (H #available) (S102). When the host ID H # is not suitable for the memorysystem 1000 (NO), the controller 1200 may output the fail signal FA tothe host 2000, and the host 2000 may change the host ID H # and outputthe host ID H # again (S101). When the received host ID H # is suitablefor the memory system 1000 (YES), the controller 1200 may determinewhether the host ID H # is an ID to be reused (S103). For example, thecontroller 1200 may check the log information and check whether an indexthe same as the received host ID H # is present. When the same index ispresent (YES), the controller 1200 may output the allocation addressA_LB mapped to the corresponding index (S104). When it is determined instep S103 that the same index is not present (NO), the controller 1200may perform the memory allocation operation to convert the host ID H #into the allocation address A_LB (S105).

The controller 1200 may search for the physical block address P_ADDusing the allocation address A_LB (S106).

When the physical block address P_ADD is selected, the controller 1200may access the storage device 1100 according to the physical blockaddress P_ADD.

FIG. 11 is a flowchart for describing the de-allocation operationaccording to an embodiment of the present disclosure.

Referring to FIG. 11, when the de-allocation request is received fromthe host 2000 (S111), the controller 1200 may determine whether theallocation address A_LB is an address that may be reused (S112). Thereuse or not may be determined according to whether the host ID H #received at the time of the allocation request has been received areference number or more. For example, when the host ID H # is an IDthat is frequently used at the time of the allocation request (YES), thecontroller 1200 may add the allocation address A_LB corresponding to thefrequently used host ID H # to the log information so as to reduce theoperation time (S113). The allocation address A_LB added to the loginformation may be directly output without a memory allocation operationwhen a corresponding host ID H # is received again at a time of asubsequent allocation request.

In step ‘S112’, when it is determined that the allocation address A_LBis an address that is not to be reused (NO), the controller 1200 mayrelease the allocation address A_LB (S114).

Next, some of the configurations for configuring the address allocator220 will be described.

FIG. 12 is a diagram for describing the allocation manager of FIG. 9.

Referring to FIG. 12, the allocation manager 310 may include a quickallocation manager 311 and a log information register 312.

When the host ID H # is received, the quick allocation manager 311 maydetermine whether the host ID H # is a suitable ID for the memory system1000. For example, when a capacity corresponding to the received host IDH # is larger than a capacity of the free memory blocks of the memorysystem 1000, the quick allocation manager 311 may output the allocationimpossible signal IMP. When the capacity corresponding to the host ID H# is smaller than the capacity of the free memory blocks of the memorysystem 1000, the quick allocation manager 311 may first transmit thereceived host ID H # (1). When the index IND corresponding to the hostID H # is not present in the log information register 312, the quickallocation manager 311 may transmit the host ID H # to the addressmanager 320 (2). That is, when information corresponding to the receivedhost ID H # is present in the log information register 312 (1), theallocation address A_LB may be directly output from the log table. Whenthe information corresponding to the received host ID H # is not presentin the log information register 312(2), the allocation address A_LB maybe output from the address manager 320.

The log information register 312 may store a log table in which the hostID H # and the allocation address A_LB are mapped. For example, in thelog information register 312, the host ID H # used at the time of aprevious allocation operation may be stored as the index IND, and theallocation address A_LB corresponding to the host ID H # may be storedas the log information LOG. When the host ID H # is received from thequick allocation manager 311, the log information register 312 may checkthe index IND corresponding to the received host ID H #.

When the index IND corresponding to the received host ID H # is presentin the index IND of the log information register 312 ({circle around(1)}), the log information register 312 may transmit the allocationaddress A_LB mapped to the corresponding index to the quick allocationmanager 311 and the map table component 330. For example, in a case inwhich a host ID 2 H2 is included the index IND and an allocation address2 2A_LB mapped to the host ID 2 H2 is included in the log informationLOG, when the received host ID H # is ‘2’, the allocation address 22A_LB mapped to the host ID 2 H2 may be transmitted to each of the quickallocation manager 311 and the map table component 330 as the allocationaddress A_LB.

When the index IND corresponding to the received host ID H # is notpresent in the index IND of the log information register 312 (2), thelog information register 312 does not output the allocation addressA_LB. When the allocation address A_LB is not output from the loginformation register 312 after the host ID H # is transmitted to the loginformation register 312 and then a predetermined time (preset time) iselapsed, the quick allocation manager 311 may transmit the host ID H #to the address manager 320. The address manager 320 receiving the hostID H # may perform the memory allocation operation to generate theallocation address A_LB and may transmit the generated allocationaddress A_LB to each of the quick allocation manager 311 and the maptable component 330. The word “preset” and “predetermined” as usedherein with respect to a parameter, such as a preset time andpredetermined time, means that a value for the parameter is determinedprior to the parameter being used in a process or algorithm. For someembodiments, the value for the parameter is determined before theprocess or algorithm begins. In other embodiments, the value for theparameter is determined during the process or algorithm but before theparameter is used in the process or algorithm.

FIG. 13 is a diagram for describing the host ID and the allocationspace.

Referring to FIG. 13, the host ID H # may have various values accordingto an allocation capacity. For example, when the logical blocks aredivided into 4 GB units, the host ID 1 H1 may mean a logical block(n+1)*4 GB, and the host ID 2 H2 may mean a logical block having acapacity corresponding to ½ of the host ID 1 H1. Here, ‘*’ sign meansmultiplication (×). For example, when it is assumed that the host ID 1H1 corresponds to a capacity of 32 GB, the host ID 2 H2 may mean alogical block having a capacity corresponding to 16 GB, which is ½ of 32GB. In the same example, each of host IDs 3 and 4 H3 and H4 may mean 8GB corresponding to ½ of the host ID 2 H2, and each of host IDs 5 to 8H5 to H8 may mean 4 GB corresponding to ½ of 8 GB.

Therefore, when the host 2000 desires to receive an allocation of acapacity of 8 GB, the host 2000 may output the host ID 3 H3 or the hostID 4 H4 to the memory system 1000.

As described above, since the host ID H # does not need much informationsuch as the logical block address and the host ID H # itself means acapacity, the host ID H # may be formed of a very small number of bits.As an embodiment, when the memory capacity of the memory system 1000 isdivided into eight logical block units, ‘n’ in 2n=8 may be the number ofbits of the host ID H #. In this case, the host ID H # may be selectedfrom 000, 001, 010, 011, 100, 101, 110, and 111. As another embodiment,when the memory capacity of the memory system 1000 is divided into eightlogical block units, the memory capacity may be divided into fourlogical block units, that is, two groups, and the host ID H # may be setfor each group. In this case, an allocation amount for the four logicalblocks may be set with the first host ID, and an allocation amount forthe remaining four logical blocks may be set with the second host ID.Here, the first host ID may be used as a main ID, and the second host IDmay be used as a sub ID.

As described above, when the memory allocation amount is implemented asthe host ID H #, the allocation request between the host 2000 and thememory system 1000 may be simplified.

The host 2000 may transmit the host ID H # corresponding to a requiredallocation amount to the memory system 1000 and the memory system 1000may perform the operation using the received host ID H # to extract thelogical block address according to an internal state of the memorysystem 1000.

FIG. 13 is a diagram for understanding a concept of the presentdisclosure. The host ID H # may be set in various methods by applying aconcept of the host ID H # of FIG. 13. Therefore, those skilled in theart will understand that a number of the host ID H # described in thefollowing embodiments may be different from a number of the host ID H #shown in FIG. 13 and capacities respectively allocated to the varioushost IDs H # may be variously set.

A method of mapping the physical block address to the logical blockaddress according to the internal state of the memory system 1000 willbe described below as follows.

FIG. 14 is a diagram for describing a method of allocating the physicalblock matched with the logical block.

Referring to FIG. 14, logical blocks LB1 to LBi (i is a positiveinteger) may be grouped into a plurality of logical block groups LBG.The logical blocks included in each of the logical block groups LBG maybe set to be respectively mapped to physical blocks MB that are capableof operating simultaneously with each other. For example, the controller1200 may respectively map the logical blocks LB included in the samelogical block group LBG to the physical blocks MB that are capable ofoperating simultaneously with each other. That is, the physical blocksMB that are capable of operating simultaneously with each other may bephysical blocks MB included in dies connected to different channels CHor the same channel CH. For example, a die group DG mapped to thelogical block group LBG may include dies connected to differentchannels. For example, when 0-th to third logical blocks LB0 to LB3 areincluded in the logical block group LBG, the 0-th logical block LB0 maybe mapped to the physical block MB included in the first die D1 amongthe dies connected to the first channel CH1, the first logical block LB1may be mapped to the physical block MB included in the first die D1among the dies connected to the second channel CH2, the second logicalblock LB2 may be mapped to the physical block MB included in the firstdie D1 among the dies connected to the third channel CH3, and the thirdlogical block LB3 may be mapped to the physical block MB included in thefirst die D1 among the dies connected to the channel CH3, respectively.As described above, when the memory blocks MB of the first dies D1connected to the different channels CH1 to CH4 are selected, since theselected memory blocks MB may be operate simultaneously, the operationtime of the memory system 1000 may be reduced. FIG. 14 shows that thefirst dies D1 are selected in all of the 0-th to third channels CH0 toCH3, but different dies included in the same channel may be selected.For example, the first to k-th die D1 to Dk of the 0-th channel CH0 maybe mapped to the same logical block group LBG. That is, the allocatedmemory blocks may be grouped into super block, and may be operated asone block logically.

Next, a method of extracting the allocation capacity and the logicalblock address from the received host ID H # will be described.

FIG. 15 is a diagram for describing a memory allocation method accordingto an embodiment of the present disclosure.

Referring to FIG. 15, the address manager 320 may perform an allocationoperation of a method of a tree TR to extract information on a logicalblock address LB # and the allocation capacity from the host ID H #. Forexample, in the embodiments shown in FIG. 15, the host ID 1 H1 maycorrespond to the highest ID. According to an embodiment, a largercapacity may be allocated as an ID is a higher ID in the tree TR, andthe number of the host IDs H # may be increased as the ID is a lower ID.The number of logical blocks allocated to the lower ID is less than thatof the adjacent upper ID by ½.

For example, the host ID 1 H1 may be an ID that may receive anallocation of the eight logical blocks LB0 to LB7, and each of the hostID 2 H2 and the host ID 3 H3 may be ID that may receive an allocation ofthe logical blocks corresponding to ½ of the host ID 1 H1. For example,when it is assumed that the host ID 1 H1 corresponds to the 0-th toseventh logical blocks LB0 to LB7, the host ID 2 H2 may correspond tothe 0-th to third logical blocks LB0 to LB3, and the host ID 3 H3 maycorrespond to the fourth to seventh logical blocks LB4 to LB7.

The host ID 2 H2 may include a host ID 4 H4 and a host ID 5 H5 as thelower ID, the host ID 4 H4 may correspond to the 0-th and first logicalblocks LB0 and LB1, and the host ID 5 H5 may correspond to the secondand third logical blocks LB2 and LB3.

The host ID 4 H4 may include a host ID 8 H8 and a host ID 9 H9 as thelower ID, the host ID 8 H8 may correspond to the 0-th logical block LB0,and the host ID 9 H9 may correspond to the first logical block LB1.

That is, the host IDs 8 to 15 H8 to H15 may correspond to the lowest IDsin the tree TR of FIG. 15 and may correspond to the logical blocks LB0to LB7 of a minimum unit, respectively.

When the memory allocation operation is performed in the method of thetree TR as the embodiments of FIG. 15, the host 2000 may output the hostID H # corresponding to the required capacity, and the memory system1000 may extract a node number ND # using the received host ID H #.Here, nodes may correspond to the logical blocks, respectively, and astart node and the number of nodes to be allocated may be extracted bythe memory allocation operation. For example, when the host ID 2 H2 isreceived, in order to extract the 0-th to third logical blocks LB0 toLB3 corresponding to the host ID 2 H2, the address manager 320 mayperform the memory allocation operation to extract a node numbercorresponding to the 0-th logical block LB0 as the start node andextract the number of nodes from the 0-th to third logical blocks LB0 toLB3. For example, when the number of nodes is extracted as four, sincethe extraction of the number of nodes as four means that four nodes areselected from the 0-th logical block LB0, which is the start node, the0-th to third logical blocks LB0 to LB3 may be allocated. That is, thenumber of nodes may be the number of the allocated logical blocks, andthe allocation capacity may be calculated according to the number ofnodes.

As described above, the memory allocation operation using the host ID H# is performed to extract the start node and the number of nodes, andthe logical blocks LB are allocated therefrom. Therefore, a separatestorage space for storing the allocation capacity corresponding to eachof the host IDs H # and the mapping information of the logical blocks isnot required. Thus, a size of the controller 1200 may be reduced. Inaddition, since the host ID H # is implemented with bits less than thatof the existing address method, the allocation operation of thecontroller 1200 may also be simplified.

FIG. 16 is a flowchart for describing an example of an operation used inthe memory allocation operation of FIG. 15.

Referring to FIG. 16, when the host ID H # is received, the addressmanager 320 may calculate a start node S_ND # and the number of nodesN_ND # by performing the following operation.

Step S161

When the allocation operation is started, 1 is set as an initial valueof the number of nodes N_ND #. That is, since the number of requirednodes N_ND # is not known when the operation is started, 1 is set as theinitial value of the number of nodes N_ND #. The number of nodes N_ND #may be calculated while the steps described later are performed.

Step S162

The host ID H # and a maximum number of nodes NDmax are calculated and avariable VA is calculated. Here, the maximum number of nodes NDmax maybe a maximum number of nodes that may be allocated in one tree, and thevariable VA may be used to calculate the number of nodes N_ND #. Forexample, the variable VA is a remainder obtained by dividing the host IDH # by a value obtained by multiplying the maximum number of nodes NDmaxby 2. Therefore, the variable VA may be 0 or a positive integer. Forexample, when the host ID H # is 3 and the maximum number of nodes NDmaxis 4, the variable VA is 3 since a quotient is 0 and the remainder is 3in 3/(4×2) formula.

Step S163

The variable VA calculated in step S162 is compared with the maximumnumber of nodes NDmax so that it is determined whether the variable VAis equal to or greater than the maximum number of nodes NDmax. As aresult of the comparison, when the variable VA is less than the maximumnumber of nodes NDmax (NO), step S164 is performed. When the variable VAis equal to or greater than the maximum number NDmax, step S166 isperformed.

Step S164

A value obtained by multiplying the number of nodes N_ND # by 2 is setto a new number of nodes N_ND #.

Step S165

A value obtained by multiplying the variable VA by 2 is set to a newvariable VA.

When the new variable VA is set, the new variable VA is compared withthe maximum number of nodes NDmax again in step S163. In this manner,steps S163 to S165 are repeated until the variable VA is equal to orgreater than the maximum number of nodes NDmax.

Step S166

The start node S_ND # is calculated as a sum of a negative value of themaximum number of nodes NDmax and the variable VA.

When the step S166 is completed, the allocation operation is ended, andthe logical blocks may be selected according to the finally calculatednumber of nodes N_ND # and the start node S_ND # among the valuescalculated in the allocation operation, the address of the selectedlogical blocks may be used as the allocation address.

Various embodiments for calculating the start node S_ND # and the numberof nodes N_ND # from the received host ID H # using the operationdescribed in FIG. 16 will be described as follows.

FIG. 17 is a first embodiment of the memory allocation operation towhich the operation of FIG. 16 is applied.

Referring to FIGS. 16 and 17, when the host ID H # received from thehost 2000 is 2, the start node S_ND # and the number of nodes N_ND #corresponding to the host ID 2 H2 may be calculated.

In step S161, the number of nodes ND # is set to 1 as the initial value.

In step S162, the variable VA is calculated by performing the operationusing the host ID H # and the maximum number of nodes NDmax. In theembodiments shown in FIG. 17, since the maximum number of nodes NDmaxthat may be allocated in one tree TR is eight (LB0 to LB7), theremainder is 2 according to 2/(8×2) operation. Therefore, the variableVA is 2.

In step S163, the variable VA is compared with the maximum number ofnodes NDmax. Since the variable VA calculated in step S162 is 2 and themaximum number of nodes NDmax is 8, the variable VA is not equal to orgreater than the maximum number of nodes NDmax (NO), and thus step S164is performed.

In step S164, since the value obtained by multiplying the number ofnodes N_ND # by 2 is the new number of nodes N_ND #, the new number ofnodes N_ND # is 2 according to 1×2 formula.

In step S165, the value obtained by multiplying the variable VA by 2 isthe new variable VA. Since the variable VA is calculated as 2 in stepS162, the new variable VA is 4 according to 2×2 formula in step S165.

In step S163, the variable VA calculated in step S165 is compared withthe maximum number of nodes NDmax. Since the variable VA is 4 and themaximum number of nodes NDmax is 8, step S164 is performed again.

In step S164, the number of nodes N_ND # is 4 according to 2×2 formula.

In step S164, the variable VA is 8 according to 4×2 formula.

In step S163, since the variable VA is 8 and the maximum number of nodesNDmax is 8, a condition 8=8 is satisfied (YES). Therefore, step S166 isperformed.

In step S166, since the start node S_ND # is a value obtained by addinga value obtained by multiplying the maximum number of nodes NDmax by −1to the variable VA, a value obtained by adding ((−1)×8) to 8 that is afinal variable VA is 0. Therefore, the start node S_ND # is 0, and thefinal number of nodes N_ND # is 4.

In FIG. 17, since the logical block LB corresponding to 0 that is thestart node S_ND is a logical block 0 LB0, four logical blocks LB0 to LB3from the logical block 0 LB0 are selected according to 4 that is thenumber of nodes N_ND4. That is, when the host ID 2 H2 is received,logical block addresses for the four logical blocks LB0 to LB3 may beselected through the operation of FIG. 16, and the address manager 320may output the selected logical block addresses as the allocationaddress A_LB.

A case in which a host ID H # different from that of FIG. 17 is receivedwill be described as an example as follows.

FIG. 18 is a second embodiment of the memory allocation operation towhich the operation of FIG. 16 is applied.

Referring to FIGS. 16 and 18, when the host ID H # received from thehost 2000 is 13, the start node S_ND # and the number of nodes N_ND #corresponding to the host ID 13 H13 may be calculated.

In step S161, the number of nodes ND # is set to 1 as the initial value.

In step S162, the variable VA is calculated by performing the operationusing the host ID H # and the maximum number of nodes NDmax. In anembodiment shown in FIG. 18, since the maximum number of nodes NDmaxthat may be allocated in one tree TR is eight (LB0 to LB7), theremainder is 13 according to 13/(8×2) operation. Therefore, the variableVA is 13.

In step S163, the variable VA is compared with the maximum number ofnodes NDmax. The variable VA calculated in step S162 is 13 and themaximum number of nodes NDmax is 8. Therefore, since the variable VA isgreater than the maximum number of nodes NDmax (YES), steps S164 andS165 are omitted and step S166 is performed.

In step S166, since the start node S_ND # is a value obtained by addinga value obtained by multiplying the maximum number of nodes NDmax by −1to the variable VA, a value obtained by adding ((−1)×8) to 13 that isthe variable VA is 5. Therefore, the start node S_ND # is 5, and thefinal number of nodes N_ND # is 1.

In FIG. 18, since the logical block LB corresponding to 5 that is thestart node S_ND is a logical block 5 LB0, one logical block LB5 from thelogical block 5 LB5 is selected according to 1 that is the number ofnodes N_ND1. That is, when the host ID 13 H13 is received, a logicalblock addresses for the one logical block LB5 may be selected throughthe operation of FIG. 16, and the address manager 320 may output theselected logical block address as the allocation address A_LB.

FIGS. 16 to 18 illustrate an embodiment in which the logical blocks areoperated by one tree. However, the logical blocks may be divided into aplurality of trees according to the storage device 1100. Otherembodiments in which the logical blocks are operated by the plurality oftrees will be described below as follows.

FIGS. 19 and 20 are diagrams for describing the memory allocation methodaccording to another embodiment of the present disclosure.

Referring to FIGS. 19 and 20, the address manager 320 may group thelogical blocks into 0-th to n-th trees Tree 0 to Tree n or T0 to Tn toperform the operation.

For example, when it is assumed that the maximum number of logicalblocks that may be allocated in one tree is 4, the 0-th to third logicalblocks LB0 to LB3 may be included in the 0-th tree T0, the fourth toseventh logical blocks LB4 to LB7 may be included in the first tree T1.

In a method in which the plurality of trees T0 to Tn are used asdescribed above, a basic node may be added to each tree. For example, inthe 0-th tree T0, the basic node may be a node corresponding to the hostID 0 H0, and in the first tree T1, the basic node may be a nodecorresponding to the host ID 8 H8. The basic nodes are not substantiallyused host IDs and may be used at the time of the de-allocationoperation. The de-allocation operation using the basic node will bedescribed later with reference to FIG. 28. The basic node may be set toa successive number from a last node of a previous tree. For example,when the host ID 7 H7 is the last node in the 0-th tree T0, the basicnode may be a node corresponding to the host ID 8 H8 in the first treeT1.

FIG. 21 is a flowchart for describing an example of the operation usedin the memory allocation method of FIG. 20.

In FIG. 21, since the plurality of trees are included, an operation forcalculating a tree number is added in comparison with the operationdescribed above with reference to FIG. 16.

Referring to FIG. 21, when the host ID H # is received, the addressmanager 320 may perform the following operation to calculate a treenumber T #, the start node S_ND #, and the number of nodes N_ND #.

Step S211

When the allocation operation is started, 1 is set as an initial valueof the number of nodes N_ND #. That is, since the number of requirednodes N_ND # is not known when the operation is started, 1 is set as theinitial value of the number of nodes N_ND #. The number of nodes N_ND #may be calculated while the steps described later are performed.

Step S212

The host ID H # and the maximum number of nodes NDmax are calculated andthe variable VA is calculated. Here, the maximum number of nodes NDmaxmay be a maximum number of nodes that may be allocated in one tree, andthe variable VA may be used to calculate the number of nodes N_ND #. Forexample, the variable VA is a remainder obtained by dividing the host IDH # by a value obtained by multiplying the maximum number of nodes NDmaxby 2. Therefore, the variable VA may be 0 or a positive integer. Forexample, when the host ID H # is 11 and the maximum number of nodesNDmax is 4, the variable VA is 3 since a quotient is 2 and the remainderis 3 in 11/(4×2) formula

Step S213

In step S213, a value obtained by dividing the quotient obtained bydividing the host ID H # by the maximum number of nodes NDmax by 2 isthe tree number T #. Therefore, the tree number T # may be 0 or apositive integer.

Step S214

The variable VA calculated in step S212 is compared with the maximumnumber of nodes NDmax so that it is determined whether the variable VAis equal to or greater than the maximum number of nodes NDmax. As aresult of the comparison, when the variable VA is less than the maximumnumber of nodes NDmax (NO), step S215 is performed. When the variable VAis equal to or greater than the maximum number NDmax, step S217 isperformed.

Step S215

A value obtained by multiplying the number of nodes N_ND # by 2 is setto a new number of nodes N_ND #.

Step S216

A value obtained by multiplying the variable VA by 2 is set to a newvariable VA.

When the new variable VA is set, step S214 is performed again. In stepS214, the new variable VA is compared with the maximum number of nodesNDmax again. In this manner, steps S214 to S216 are repeated until thevariable VA is equal to or greater than the maximum number of nodesNDmax.

Step S217

The start node S_ND # is calculated as a value obtained by adding avalue obtained by multiplying a value (T #−1) obtained by subtracting 1from the tree number T # by the maximum number of nodes NDmax to thevariable VA. That is, in step S217, a value obtained by calculatingVA+(T #−1)×NDmax may be calculated as the start node S_ND #.

When the S217 step is completed, the allocation operation is ended, andthe logical blocks may be selected according to the finally calculatedtree number T #, number of nodes N_ND #, and start node (S_ND #) amongthe values calculated in the allocation operation. The address of theselected logical blocks may be used as the allocation address.

Various embodiments for calculating the tree number T #, the start nodeS_ND #, and the number of nodes N_ND # from the received host ID H #using the operation described in FIG. 21 will be described as follows.

FIG. 22 is a diagram for describing a first embodiment of the memoryallocation operation to which the operation of FIG. 21 is applied.

Referring to FIGS. 21 and 22, when the host ID H # received from thehost 2000 is 1, the tree number T #, the start node S_ND #, and thenumber of nodes N_ND # corresponding to the host ID 1 H1 may becalculated.

In step S211, the number of nodes ND # is set to 1 as the initial value.

In step S212, the variable VA is calculated by performing the operationusing the host ID H # and the maximum number of nodes NDmax. In anembodiment shown in FIG. 22, since the maximum number of nodes NDmaxthat may be allocated in each tree T0 or T1 is four, the remainder is 1according to 1/(4×2) operation. Therefore, the variable VA is 1.

In step S213, the quotient obtained by dividing the host ID H # by themaximum number of nodes NDmax is divided by 2 again. The finallycalculated quotient in formula of step S213 is the tree number T #. Inan embodiment of FIG. 22, since the host ID H # is 1 and the maximumnumber of nodes NDmax is 4, 0 is calculated as a quotient of ¼, and aquotient obtained by dividing 0 by 2 is 0. Therefore, the tree number T# is 0. Thus, the 0-th tree T0 is selected.

In step S214, the variable VA is compared with the maximum number ofnodes NDmax. Since the variable VA calculated in step S212 is 1 and themaximum number of nodes NDmax is 4, the variable VA is not equal to orgreater than the maximum number of nodes NDmax (NO), and thus step S215is performed

In step S215, since the value obtained by multiplying the number ofnodes N_ND # by 2 is the new number of nodes N_ND #, the new number ofnodes N_ND # is 2 according to 1×2 formula

In step S216, the value obtained by multiplying the variable VA by 2 isthe new variable VA. Since the variable VA is calculated as 1 in stepS216, the new variable VA is 2 according to 1×2 formula in step S216.

In step S214, the variable VA calculated in step S216 is compared withthe maximum number of nodes NDmax. Since the variable VA is 2 and themaximum number of nodes NDmax is 4, step S215 is performed again.

In step S215, the number of nodes N_ND # is 4 according to 2×2 formula.

In step S216, the variable VA is 4 according to 2×2 formula.

In step S214, since the variable VA is 4 and the maximum number of nodesNDmax is 4, a condition 4=4 is satisfied (YES). Therefore, step S217 isperformed

In step S217, the start node S_ND # is a value obtained by adding avalue obtained by multiplying a value (T #−1) obtained by subtracting 1from the tree number T # by the maximum number of nodes NDmax to thevariable VA. Therefore, a value obtained by adding (−1)×4 to 4 that isthe variable VA is 0. Therefore, the start node S_ND # is 0, and thefinal number of nodes N_ND # is 4.

The tree number T #, the start node S_ND #, and the number of nodes ND #calculated according to the operation described above are 0, 0, and 4,respectively. Therefore, the logical blocks LO to L3 included in thefourth logical block from the 0-th logical block LB0 included in the0-th tree T0 by the host ID 1 H1 may be selected.

That is, when the host ID 1 H1 is received, logical block addresses forthe four logical blocks LB0 to LB3 may be selected through the operationof FIG. 21, and the address manager 320 may output the selected logicalblock address as the allocation address A_LB.

A case in which a host ID H # different from that of FIG. 22 is receivedwill be described as an example as follows.

FIG. 23 is a diagram for describing a second embodiment of the memoryallocation operation to which the operation of FIG. 21 is applied.

Referring to FIGS. 21 and 23, when the host ID H # received from thehost 2000 is 10, the tree number T #, the start node S_ND #, and thenumber of nodes N_ND # corresponding to the host ID 10 H10 may becalculated.

In step S211, the number of nodes ND # is set to 1 as the initial value.

In step S212, the variable VA is calculated by performing the operationusing the host ID H # and the maximum number of nodes NDmax. In anembodiment shown in FIG. 23, since the maximum number of nodes NDmaxthat may be allocated in each tree TR0 or TR1 is four, the remainder is2 according to 10/(4×2) operation. Therefore, the variable VA is 2.

In step S213, the tree number T3 is calculated by operating the host IDH # and the maximum number of nodes NDmax. Since the quotient is 1according to (10/4)/2 formula, the tree number T # is 1.

In step S214, the variable VA is compared with the maximum number ofnodes NDmax. Since the variable VA calculated in step S212 is 2 and themaximum number of nodes NDmax is 4, the variable VA is less than themaximum number of nodes NDmax (NO). Therefore, step S215 is performed.

In step S215, since the value obtained by multiplying the number ofnodes N_ND # by 2 is the new number of nodes N_ND #, the new number ofnodes N_ND # is 2 according to 1×2 formula.

In step S216, a value obtained by multiplying the variable VA by 2 isthe new variable VA. Since the variable VA is calculated as 2 in stepS212, the new variable VA is calculated as 4 according to 2×2 formula instep S216.

In step S214, the variable VA calculated in step S216 is compared withthe maximum number of nodes NDmax. Since the variable VA is 4 and themaximum number of nodes NDmax is 4, the condition of 4=4 is satisfied(YES). Therefore, step S217 is performed.

In step S217, the start node S_ND # is the value obtained by adding thevalue obtained by multiplying the value obtained by subtracting 1 fromthe tree number T # by the maximum number of nodes NDmax to the variableVA. Therefore, a value obtained by adding (1-1)×4 to 4 that is thevariable VA is 4. Thus, the start node S_ND # is 4, and the final numberof nodes N_ND # is 2.

The tree number T #, the start node S_ND #, and the number of nodes ND #calculated according to the operation described above are 1, 4, and 2,respectively. Therefore, the logical blocks L4 and L5 included in thesecond logical block from the fourth logical block LB4 included in thefirst tree T1 by the host ID 10 H10 may be selected.

That is, when the host ID 10 H10 is received, logical block addressesfor the two logical blocks LB4 and LB5 may be selected through theoperation of FIG. 21, and the address manager 320 may output theselected logical block address as the allocation address A_LB.

In the embodiments described above, when the host 2000 outputs one hostID H #, the controller 1200 of the memory system 1000 performs theallocation operation using the received host ID H # to select thelogical blocks.

In the following embodiments, a method in which the host 2000 outputs aplurality of host IDs, and accordingly, the controller 1200 selects thelogical blocks is described.

FIG. 24 is a diagram for describing a host ID policy for requesting thememory allocation from the host to the memory system.

Referring to FIG. 24, when the host 2000 requests the memory allocationto the memory system 1000, the host 2000 may output two or more host IDs1H # and 2H # according to a host ID policy to request the memoryallocation. The host ID policy may include information on the capacityof the logical block, the number of the tree, the number of the hostIDs, and the like, and such information may be shared with the host 2000and the memory system 1000. The host 2000 may request the allocation orrequest the de-allocation to the memory system 1000 according to thehost ID policy shared with the memory system 1000. FIG. 24 shows anembodiment in which the host 2000 outputs the two host IDs 1H # and 2H #to the memory system 1000, and the number of the host IDs is changeableaccording to an embodiment.

The host 2000 outputs the first and second host IDs 1H # and 2H # asdifferent IDs so that the logical blocks are not repetitively allocated.The memory system 1000 may perform allocation operations respectivelyusing the first host ID 1H # and the second host ID 2H # to selectlogical blocks allocated to the respective host IDs. For example, thememory system 1000 may select the logical blocks allocated according toan operation result using the first host ID 1H #, and may select thelogical blocks allocated according to an operation result using thesecond host ID 2H #.

FIG. 25 is a diagram for describing embodiments of the host ID policy ofFIG. 24.

Referring to FIG. 25, the host 2000 and the memory system 1000 maydivide the storage capacity of the memory system 1000 into one or aplurality of logical blocks according to a preset host ID policy, andmay perform the memory allocation operation according to the host IDpolicy. Alternatively, on the contrary, the storage capacity of thememory system 1000 may be divided into one or a plurality of logicalblocks, and the host ID policy may be set accordingly. The word “preset”as used herein with respect to a parameter, such as a preset host IDpolicy, means that a value for the parameter is determined prior to theparameter being used in a process or algorithm. For some embodiments,the value for the parameter is determined before the process oralgorithm begins. In other embodiments, the value for the parameter isdetermined during the process or algorithm but before the parameter isused in the process or algorithm.

For example, under a first host ID policy 1, the host 2000 may requestthe allocation to the memory system 1000 using one host ID, under asecond host ID policy 2, the host 2000 may request the allocation to thememory system 1000 using two different host IDs, and under a third hostID policy 3, the host 2000 may request the allocation to the memorysystem 1000 using three different host IDs. In a policy using aplurality of host IDs such as the second or third host ID policy 2 or 3,allocable capacities may be set differently for the respective host IDs.For example, in the second host ID policy 2, the capacity that may beallocated to the first host ID 1H # and the capacity that may beallocated to the second host ID 2H # may be the same as 16 GB. Asanother example, in the third host ID policy 3, the capacity that may beallocated to the first host ID 1H # may be set as 16 GB and the capacitythat may be allocated to the second and third host IDs 2H # and 3H # maybe set as 8 GB equally.

To this end, the host 2000 and the memory system 1000 share the host IDpolicy with each other. For example, since different memory systems 1000may have different allocable total capacities, the host ID policy may bepreferentially set in the memory system 1000. For example, when thememory system 1000 and the host 2000 are connected to each other, thehost 2000 may request various kinds of policy information to the memorysystem 1000, and the memory system 1000 may transmit the policyinformation applied to various operations to the host 2000 according tothe request of the host 2000. At this time, the host ID policy set inthe memory system 1000 may be transmitted to the host 2000. The host2000 may generate the host ID corresponding to a required allocationcapacity according to the host ID policy transmitted from the memorysystem 1000 and output the generated host ID to the memory system 1000.

FIG. 26 is a diagram for describing an embodiment of the second host IDpolicy among the embodiments described with reference to FIG. 25.

Referring to FIG. 26, when it is assumed that the capacity of onelogical block LB is 4 gigabytes, all logical blocks selected accordingto the first host ID 1H # and the second host ID 2H # may be allocated.For example, when the first host ID 1 H1 and the second host ID 10 H10are received, the address manager 320 of the controller 1200 may performthe allocation operation to select the four logical blocks LB0 to LB3corresponding to the first host ID 1 H1 and the two logical blocks LB4and LB5 corresponding to the second host ID 10 H10. Since the capacityof the four logical blocks LB0 to LB3 is 16 GB and the capacity of thetwo logical blocks LB4 and LB5 is 8 GB, the host 2000 requests memoryallocation of 24 GB. In addition, the host 2000 may use different hostIDs even though the same capacity allocation is requested. For example,differently from the embodiments described above, the host 2000 mayoutput the first host ID 2 H2 and the second host ID 9 H9 for memoryallocation of 24 GB. In this case, the address manager 320 may performthe allocation operation to select the two logical blocks LB0 and LB1corresponding to the first host ID H2 and the four logical blocks LB4 toLB7 corresponding to the second host ID 9 H9.

FIG. 27 is a diagram for describing an operation of the map tablecomponent of FIG. 9.

Referring to FIG. 27, when the address manager 320 outputs theallocation address A_LB as described above, the map table component 330may output the physical block address P_ADD mapped to the allocationaddress A_LB. To this end, the map table component 330 may include aregister for storing a map table in which the logical block addressL_ADD and the physical block address P_ADD are mapped.

The logical block address L_ADD of the map table may include the logicalblock address according to the host ID policy, and the physical blockaddress P_ADD may include the address of the allocable memory blocksamong the memory blocks included in the storage device 1100. Inparticular, the physical block address P_ADD may be mapped to an addressat which the logical blocks included in the same tree may operatesimultaneously, in consideration of a tree structure.

An operation of mapping the physical block address P_ADD to the logicalblock address L_ADD of the map table may be performed by the processor(210 of FIG. 2). However, in an embodiment, the physical block addressP_ADD may be mapped to the logical block address L_ADD so that differentphysical blocks that are allocated according to the request of the host2000 may operate simultaneously. Such an address mapping operation maybe performed by the processor (210 of FIG. 2) included in the controller1200. The processor 210 may frequently update the map table by mappingthe physical block address P_ADD to the logical block address L_ADDaccording to a state of the free memory blocks of the storage device1100. For example, the processor 210 may update the map table at a timeof a background operation of the memory system 1000 including theprocessor 210, or may update the map table when the allocation requestis received from the host 2000.

When the address manager 320 performs the allocation operation to outputthe address of the 0-th and first logical blocks LB0 and LB1 as theallocation address A_LB, the map table component 330 may output thefirst memory block MB1 of the first die D1 mapped to the 0-th logicalblock LB0 and the second memory block MB2 of the second die D2 mapped tothe first logical block LB1 as the physical block address P_ADD from thestored map table.

In an described above, a method of calculating the start node S_ND #,the number of nodes ND #, and the tree number T # based on the host ID H# has been described. Next, a method of calculating the host ID H #based on the start node S_ND # will be described in contrast to anembodiment described above. The method may be used when calculating thehost ID by using information on the allocated area at a time ofoperation such as the de-allocation.

FIG. 28 is a flowchart for describing an example of an operation ofcalculating the host ID using the start node.

Referring to FIG. 28, the address manager 320 may calculate the host IDH # based on the start node S_ND # calculated by the above-describedallocation operation.

Step S281

When the de-allocation operation is started, 1 is set as an initialvalue of the variable VA. The variable VA means the number of successivelogical blocks that may be simultaneously processed.

Step S282

The start node S_ND # and the maximum number of nodes NDmax arecalculated and thus the tree number T # is calculated. For example, thequotient obtained by dividing the start node S_ND # by the maximumnumber of nodes NDmax is the tree number T #.

Step S283

The basic node B # is calculated by multiplying the value obtained bymultiplying the tree number T # calculated in step S282 by 2 by themaximum number of nodes NDmax. The basic node B # is the first host IDof each tree, and the host ID designated as the existing node is notused at the time of the memory allocation operation. That is, the basicnode B # is used only in the de-allocation operation and is not used inthe memory allocation operation.

Step S284

A node turn number N # is calculated by adding the remainder obtained bydividing the start node S_ND # by the maximum number of nodes NDmax tothe maximum number of nodes NDmax. At the time of the de-allocationoperation, the node turn N # is used to search for a number of the nodeto which the host ID H # corresponds from the basic node B # of thecalculated tree number T #.

Step S285

It is determined whether the host ID H # of the calculated node turn N #is the allocated host ID.

When the host ID H # of the calculated node turn N # is not theallocated host ID (NO), step S286 is performed. When the host ID H # isthe allocated host ID (YES), step S288 is performed.

Step S286

A value obtained by multiplying the variable VA by 2 is set as the newvariable VA.

Step S287

A quotient obtained by dividing the node turn N # by 2 is set as a newnode turn N #.

When the node turn N # is newly set, step S285 is performed again usingthe newly set node turn N #.

Step S288

When it is determined in step S285 that the host ID corresponding to thenode turn N # is allocated (YES), a node calculated by adding the basicnode B # and the node turn N # is the host ID H #.

An embodiment for calculating the host ID H # from the start node S_ND #using the operation described with reference to FIG. 28 will bedescribed as follows.

FIG. 29 is a diagram for describing an embodiment of a method ofcalculating the host ID to which the operation of FIG. 28 is applied.

Referring to FIGS. 28 and 29, when the start node S_ND # is 0 LB0, thehost ID H # may be calculated by applying the operation described withreference to FIG. 28.

In step S281, 1 is set as the initial value of the variable VA.

In step S282, an operation using the start node S_ND # and the maximumnumber of nodes NDmax is performed and thus the tree number T # iscalculated. In an embodiment of FIG. 29, since the start node S_ND # is0 (1) and the maximum number of nodes NDmax is 4, the quotient is 0according to 0/4 operation. Therefore, the tree number T # is 0 (2).

In step S283, the value obtained by multiplying the value obtained bymultiplying the tree number T # by 2 and the maximum number of nodesNDmax is the basic node B #. In an embodiment, since the tree number T #is 0, the basic node B # is 0 (3). That is, the host ID 0 H0 is thebasic node B #.

In step S284, since the start node S_ND # is 0 and the maximum number ofnodes NDmax is 4, the remainder obtained by dividing the start node S_ND# by the maximum number of nodes NDmax is 0. Since the value obtained byadding the maximum number of nodes NDmax to the remainder is the nodeturn N #, the node turn N # is 4 according to 0+4 operation.

In step S285, it is determined whether the host ID H # corresponding tothe calculated node turn N # is an allocated ID. For example, since thecalculated basic node B # is 0 and the node turn N # is 4, it isdetermined whether the host ID 4 H4 corresponding to a fourth node fromthe host ID 0 H0 is the allocated ID. Although the 0-th logical blockLB0 is allocated to the host ID 4 H4, since it is determined that otherlogical blocks are allocated in addition to the 0-th logical block LB0according to the number of currently allocated logical blocks (NO), stepS286 is performed.

In step S286, the variable VA is multiplied by 2, and the new variableVA is 2.

In step S287, when the node turn N # is divided by 2, the quotient ofthe 4/2 operation is 2. Therefore, the new node turn N # is 2 (4).

In step S285, since the newly calculated node turn N # is 2, it ischecked whether or not the host ID 2 H2 corresponding to a second nodefrom the host ID 0 H0 corresponding to the basic node B #0 is allocated.Since the two logical blocks LB0 and LB1 are allocated to the host ID 2H2, the number of the logical blocks is the same as the number oflogical blocks currently allocated to the calculated tree number T #.When the number of allocated logical blocks is the same as describedabove (YES), step S288 is performed.

In step S288, when the basic node B # and the node turn N # are addedtogether, the host ID 2 H2 is calculated according to 0+2 operation.

As described above, the host ID H # and the variable VA may becalculated using the starting node S_ND # of the allocated logicalblocks and the number of logical blocks allocated in the selected tree.Such an operation may be used for outputting the host ID H #corresponding to the allocated logical blocks or searching for the hostID H # corresponding to the logical blocks allocated at the time of theoperation (for example, a background operation) performed in the memorysystem. For example, when a block where an error occurs is detected whenan operation such as garbage collection, read reclaim, bad blockmanagement, or wear-leveling is performed in the memory system, theabove-described operation may be used for searching for the node numberor host ID H # corresponding to the detected block. In addition, sincethe number of successive logical blocks that may be simultaneouslyprocessed may be grasped from the calculated variable VA, an operationsuch as address mapping may also be performed based on the number ofsuccessive logical blocks.

The controller 1200 that performs the above-described memory allocationoperation and de-allocation operation may be applied to various memorysystems as follows.

FIGS. 30 to 33 are diagrams for describing another embodiment of thememory system including the controller shown in FIG. 2.

Referring to FIG. 30, a memory system 30000 may be implemented as acellular phone, a smartphone, a tablet PC, a personal digital assistant(PDA) or a wireless communication device.

The memory system 30000 may include the storage device 1100 and thecontroller 1200 capable of controlling the operation of the storagedevice 1100. The controller 1200 may control a data access operation,e.g., a program, erase, or read operation, of the storage device 1100under the control of the host 2000.

Data programmed in the storage device 1100 may be output through adisplay 3200 under the control of the controller 1200.

A radio transceiver 3300 may transmit and receive radio signals throughan antenna ANT. For example, the radio transceiver 3300 may convert aradio signal received through the antenna ANT into a signal that may beprocessed by the host. Therefore, the host may process the signal outputfrom the radio transceiver 3300 and transmit the processed signal to thecontroller 1200 or the display 3200. The controller 1200 may transmitthe signal processed by the host 2000 to the storage device 1100. Inaddition, the radio transceiver 3300 may convert a signal output fromthe host into a radio signal, and output the converted radio signal toan external device through the antenna ANT. An input device 3400 may bea device capable of inputting a control signal for controlling theoperation of the processor 3100 or data to be processed by the host. Theinput device 3400 may be implemented as a pointing device such as atouch pad or a computer mouse, a keypad, or a keyboard. The host maycontrol an operation of the display 3200 so that data output from thecontroller 1200, data output from the radio transceiver 3300, or dataoutput from the input device 3400 is output through the display 3200.

Referring to FIG. 31, a memory system 40000 may be implemented as apersonal computer (PC), a tablet PC, a net-book, an e-reader, a personaldigital assistant (PDA), a portable multimedia player (PMP), an MP3player, or an MP4 player.

The memory system 40000 may include the storage device 1100 and thecontroller 1200 capable of controlling a data process operation of thestorage device 1100.

The host may output data stored in the storage device 1100 through adisplay 4300, according to data input through an input device 4200. Forexample, the input device 4200 may be implemented as a point device suchas a touch pad or a computer mouse, a keypad, or a keyboard.

The host may control the overall operation of the memory system 40000and control the operation of the controller 1200.

Referring to FIG. 32, a memory system 50000 may be implemented as animage processing device, e.g., a digital camera, a portable phoneprovided with a digital camera, a smartphone provided with a digitalcamera, or a tablet PC provided with a digital camera.

The memory system 50000 may include the storage device 1100 and thecontroller 1200 capable of controlling a data process operation, e.g., aprogram, erase, or read operation, of the memory device 1100.

An image sensor 5200 of the memory system 50000 may convert an opticalimage into digital signals. The converted digital signals may betransmitted to the host. Under the control of the host, the converteddigital signals may be output through a display 5300 or stored in thestorage device 1100 through the controller 1200. Data stored in thestorage device 1100 may be output through the display 5300 under thecontrol of the host.

Referring to FIG. 33, a memory system may include the host 2000 and amemory card 70000.

The memory card 70000 may be implemented as a smart card. The memorycard 70000 may include the storage device 1100, the controller 1200, anda card interface 7100.

The controller 1200 may control data exchange between the storage device1100 and the card interface 7100. According to an embodiment, the cardinterface 7100 may be a secure digital (SD) card interface or amulti-media card (MMC) interface, but is not limited thereto. Inaddition, the card interface 7100 may interface data exchange betweenthe host 2000 and the controller 1200 according to a protocol of thehost 2000. According to an embodiment, the card interface 7100 maysupport a universal serial bus (USB) protocol, and an interchip (IC)-USBprotocol. Here, the card interface 7100 may refer to hardware capable ofsupporting a protocol that is used by the host 2000, software installedin the hardware, or a signal transmission method.

Although the present disclosure describes many embodiments, variouschanges and modifications may be made without departing from the scopeand technical spirit of the disclosure. Therefore, the scope of thepresent disclosure should not be limited to the above-describedembodiments, but should be determined by the following claims and theequivalents of the claims of the present disclosure.

What is claimed is:
 1. A controller comprising: an allocation managerconfigured to determine whether a host identification (ID) output from ahost is an allocable ID; an address manager configured to perform anallocation operation using the host ID to select logical blockscorresponding to the host ID when the host ID is received from theallocation manager, and output an address of the logical blocks as anallocation address; and a map table component configured to store a maptable in which logical block addresses and physical block addresses arerespectively mapped, select a logical block address corresponding to theallocation address, and output the physical block address mapped to theselected logical block address.
 2. The controller according to claim 1,wherein the host ID is set for each capacity of logical blocks dividedaccording to a host ID policy.
 3. The controller according to claim 2,wherein one or a plurality of host IDs are output from the hostaccording to the host ID policy.
 4. The controller according to claim 1,wherein the allocation manager determines whether the host ID is theallocable ID according to whether the host ID conforms to a prescribedhost ID policy or whether a capacity of a memory requested to beallocated is an allocable capacity.
 5. The controller according to claim4, wherein the host ID policy includes information on a capacity of thelogical block, the number of trees, and the number of host IDs, and theinformation is shared with the host and a memory system.
 6. Thecontroller according to claim 4, wherein the allocation manager outputsan allocation impossible signal to the host when the host ID isdetermined as an unallocable ID, outputs the host ID to the addressmanager so that the allocation operation is performed when the host IDis determined as the allocable ID, and outputs an allocation completionsignal to the host when the allocation address is received after theallocation operation is completed.
 7. The controller according to claim1, wherein the address manager performs the allocation operation basedon a structure in which a plurality of nodes are connected in a tree. 8.The controller according to claim 7, wherein a method in which theplurality of IDs are associated with one another in the tree structureincludes a configuration in which a plurality of lower IDs arecorresponded to a higher ID among the IDs.
 9. The controller accordingto claim 8, wherein the host ID corresponding to a highest ID among theIDs corresponds to all logical blocks included in the tree, and the hostIDs corresponding to a lowest ID among the IDs correspond to the logicalblocks included in the tree, respectively.
 10. The controller accordingto claim 1, wherein the map table component includes a registerconfigured to store the map table.
 11. The controller according to claim10, wherein the physical block addresses mapped to the logical blockaddresses are updated according to a state of a storage devicecontrolled by a controller, in the map table.
 12. The controlleraccording to claim 1, wherein the address manager calculates the host IDusing the allocation address at a time of a de-allocation operation. 13.A controller comprising: a processor configured to map physical blockaddresses corresponding to free memory blocks to logical block addressesso that the free memory blocks that are operable simultaneously witheach other are included in the same tree; an address allocatorconfigured to perform an allocation operation based on a configurationof the tree to select logical blocks corresponding to a host ID andoutput addresses of the free memory blocks mapped to addresses of thelogical blocks; and a memory interface that accesses physical blockscorresponding to addresses of the free memory blocks.
 14. The controlleraccording to claim 13, wherein the physical blocks corresponding to theaddresses of the free memory blocks forms a super block that is operatedas one block logically.
 15. The controller according to claim 13,wherein, when blocks selected by the host ID among the free memoryblocks are generated, the processor maps the addresses of the physicalblocks excluding the selected blocks to the logical block addresses. 16.The controller according to claim 13, wherein the address allocatorcomprises: an allocation manager configured to determine whether or notthe host ID is available and stores log information on frequently usedIDs among the host IDs than a reference number; an address managerconfigured to perform an allocation operation using the host ID toselect logical blocks corresponding to the host ID when the host ID isreceived from the allocation manager, and output an address of thelogical blocks as an allocation address; and a map table componentconfigured to store a map table in which the logical block addresses andthe physical block addresses are respectively mapped, select a logicalblock address corresponding to the allocation address, and output thephysical block address mapped to the selected logical block address. 17.The controller according to claim 16, wherein the log informationincludes logical block addresses mapped to frequently used IDs among thehost IDs.
 18. The controller according to claim 16, wherein theallocation manager comprises: a log information register configured tostore the log information; and a quick allocation manager configured tocheck whether an ID corresponding to a received host ID is present amongIDs stored in the log information register when the host ID is received,directly output log information mapped to a corresponding ID when thecorresponding ID is present, and transmit the host ID to the addressmanager when the corresponding ID is not present.
 19. The controlleraccording to claim 16, wherein the address manager calculates theaddresses of the logical blocks by performing the allocation operationusing the host ID, or calculates the host ID by performing ade-allocation operation using the addresses of the logical blocks. 20.The controller according to claim 16, wherein the map table componentincludes a register in which a map table in which the logical blockaddress and the physical block address are mapped is stored.
 21. Thecontroller according to claim 20, wherein the addresses stored in themap table are updated by control of the processor.
 22. The controlleraccording to claim 21, wherein the processor updates the map table at atime of a background operation of a memory system including theprocessor or updates the map table when an allocation request isreceived from a host.
 23. A memory system comprising: a plurality ofmemory blocks; and a controller configured to receive a host IDaccording to a host ID policy in which the memory blocks are dividedinto logical block units, calculate an allocation address based on thereceived host ID, and access allocated memory blocks among the memoryblocks according to physical block addresses mapped to the allocationaddress.
 24. The memory system according to claim 23, wherein the hostID is differently implemented according to the number of requiredlogical blocks.
 25. The memory system according to claim 23, wherein thecontroller stores log information corresponding to the host ID receiveda reference number or more when the host ID is received the referencenumber or more, and allocates memory blocks according to the loginformation without an allocation operation when the host ID that isreceived the reference number or more is received.
 26. The memory systemaccording to claim 23, wherein, when an error occurs in the allocatedmemory blocks, the controller performs a de-allocation operation usingthe allocation address to extract the host ID.
 27. A method of operatinga memory system, the method comprising: calculating a start node and thenumber of logical blocks by performing an allocation operation using ahost ID when the host ID divided into logical block units is received;generating an address of the logical blocks allocated according to thestart node and the number as an allocation address; detecting a physicalblock address mapped to the allocation address; and allocating memoryblocks according to the physical block address.
 28. The method accordingto claim 27, wherein the allocation operation is performed based on atree in which IDs are connected through nodes.
 29. The method accordingto claim 28, wherein the tree has a structure in which a plurality oflower IDs are connected to a higher ID among the IDs.
 30. The methodaccording to claim 29, wherein all logical blocks included in a selectedID are allocated when one of the IDs is selected as a result of theallocation operation.